CadenceCONNECT: Jasper User Group San Jose

Nitish Sharma has more than 7 years of experience working in CPU Formal Verification. Currently, he is leading the Cache Coherency Formal Verification efforts for Last Level Cache in Qualcomm Nuvia-CPUs. Before joining Qualcomm, he was part of FV teams at Apple Inc and Oski Technologies. He has extensive experience working on model checking, and equivalence verification methodologies.

Prakeerthi Jallipalli has over 17 years of experience as an ASIC Verification engineer, specializing in both UVM Simulation and Formal verification methodologies. He has diverse verification experience working at IP, Subsystem and SoC levels. Ten years ago, he got introduced to Formal verification, which quickly became his passion. He previously worked at companies including Micron, Qualcomm and Microsoft. Prakeerthi joined Intel’s Xeon SoC team i.e., Server IP and Firmware Group(SIFG) in 2020 to lead the formation of a Formal verification team. At Xeon SoC team of Intel, he now oversees all Formal Verification activities across Xeon product lines, significantly reducing Pre-Si validation time. He holds certifications on Leadership programs from UC Berkeley & Harvard University, and his career mantra is "Stay Curious and Keep Learning". In his leisure time, he enjoys getting lost in a good book, getting lost on hiking trails, and getting lost in new places to visit—he’s really into the whole “getting lost” thing!

Mandar Munishwar has been working as a formal verification engineer at Google for the last 6 years. Prior to that he was doing formal verification at Qualcomm. He has been working in the formal verification industry for more than 15 years.

Ghaith Bany Hamad holds a PhD in multilevel formal verification methods. He then worked as an AI researcher at Stanford. For the past three years, he has been a formal verification engineer at Nvidia. Before that, he did formal verification at AMD. He has over 12 years of experience in the formal verification industry and academia.

John O’Leary is a senior principal engineer in Intel’s performance-core design team, working on arithmetic and datapath formal verification. In his 29 years at Intel he’s been involved with FV research, tool architecture and development, methodology innovation and application in the trenches.

Christian Appold works as a Research Engineer in the field of Microprocessor R&D at automotive supplier DENSO in Munich. He studied Computer Science at University of Würzburg and did his PhD in the field of Model Checking based formal verification of parallel software also at University of Würzburg. Afterwards he worked for companies like ARM or Dialog Semiconductor (now Renesas) in the field of formal verification of hardware, as a research engineer or in product development. DENSO is developing and selling its own RISC-V processors and to be successful the security of its processors is very important, especially in automotive applications. As formal verification allows exhaustive verification of hardware, it is mandatory for security of DENSO processors to apply formal verification for verification of their security-critical functionality and our corresponding work is presented in this talk.

Bhaskar has 20 yrs of experience in verification spanning across all levels of the design with various methods including simulation , formal and emulation. He has passion towards identifying the best verification method for a given design while experimenting with latest techniques available. Previously he worked in companies like Texas Instruments, Smartplay and Cadence design systems and currently taken up the challenge of verifying RISC-V design using formal verification in Condor Computing – a start-up.